fix internal naming

diff --git a/smh_ac440b_board.py b/smh_ac440b_board.py
index 7904deae662bda31321d62a3a5a47ff3c6af30a1..7b4fb41ddbf285f5ba400c3b59f95e68d3a36322 100644 (file)
--- a/smh_ac440b_board.py
+++ b/smh_ac440b_board.py
@@ -9,7 +9,7 @@ _io = [
     # Persistent I/O - fixed on the AC440B itself ------------------------------
     
     # Clk
     # Persistent I/O - fixed on the AC440B itself ------------------------------
     
     # Clk

-    ("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
+    ("clk50",   0, Pins("T2"),  IOStandard("3.3-V LVTTL")),

 
     # D1-D4
     ("u_led_n", 0, Pins("V22"), IOStandard("3.3-V LVTTL")),
 
     # D1-D4
     ("u_led_n", 0, Pins("V22"), IOStandard("3.3-V LVTTL")),


@@ -18,9 +18,9 @@ _io = [
     ("u_led_n", 3, Pins("U21"), IOStandard("3.3-V LVTTL")),
 
     # RST, K1-K2
     ("u_led_n", 3, Pins("U21"), IOStandard("3.3-V LVTTL")),
 
     # RST, K1-K2

-    ("rst_n", 0, Pins("D2"), IOStandard("3.3-V LVTTL")),
-    ("u_key_n",    0, Pins("W1"), IOStandard("3.3-V LVTTL")),
-    ("u_key_n",    1, Pins("V1"), IOStandard("3.3-V LVTTL")),
+    ("rst_n",   0, Pins("D2"),  IOStandard("3.3-V LVTTL")),
+    ("u_key_n", 0, Pins("W1"),  IOStandard("3.3-V LVTTL")),
+    ("u_key_n", 1, Pins("V1"),  IOStandard("3.3-V LVTTL")),

 
     # Persistent I/O end -------------------------------------------------------
 
 
     # Persistent I/O end -------------------------------------------------------
 

diff --git a/smh_ac440b_target.py b/smh_ac440b_target.py
index 5b605b92e9fbab22100ba083ecbdf3122b815ca2..4a26f8d90c3d5931d4d468757b25aff4b0167867 100755 (executable)
--- a/smh_ac440b_target.py
+++ b/smh_ac440b_target.py
@@ -10,7 +10,7 @@ from litex.soc.integration.builder import *
 from litex.soc.interconnect.csr import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.soc.interconnect.csr import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 

-import mmuless_board
+import smh_ac440b_board

 
 # CRG --------------------------------------------------------------------------
 
 
 # CRG --------------------------------------------------------------------------
 


@@ -54,7 +54,7 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=50e6,
         **kwargs):
 
     def __init__(self, sys_clk_freq=50e6,
         **kwargs):
 

-        platform = mmuless_board.Platform()
+        platform = smh_ac440b_board.Platform()

 
         # CRG ------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)
 
         # CRG ------------------------------------------------------------------
         self.crg = _CRG(platform, sys_clk_freq)


@@ -81,12 +81,11 @@ class BaseSoC(SoCCore):
         self.comb += If(self.crg.cd_sync.rst, self.cpu.reset.eq(1))
 
 
         self.comb += If(self.crg.cd_sync.rst, self.cpu.reset.eq(1))
 
 

-

 # Build ------------------------------------------------------------------------
 
 def main():
     from litex.build.parser import LiteXArgumentParser
 # Build ------------------------------------------------------------------------
 
 def main():
     from litex.build.parser import LiteXArgumentParser

-    parser = LiteXArgumentParser(platform=mmuless_board.Platform, description="LiteX SoC on SiMiaoHub AC440B")
+    parser = LiteXArgumentParser(platform=smh_ac440b_board.Platform, description="LiteX SoC on SiMiaoHub AC440B")

     parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
     args = parser.parse_args()
     
     parser.add_target_argument("--sys-clk-freq", default=50e6, type=float, help="System clock frequency.")
     args = parser.parse_args()